• Merrin Mary Solomon M.Tech Student, Amity School of Engineering & Technology Amity University Haryana, Gurugram, India
  • Neeraj Gupta Assistant Professor, Amity School of Engineering & Technology Amity University Haryana, Gurugram, India
  • Rashmi Gupta Assistant Professor, Amity School of Engineering & Technology Amity University Haryana, Gurugram, India
Keywords: Gate Diffusion Input, Full Adder, Power Dissipation, CMOS Logic, Delay


Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.


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How to Cite
Solomon, M. M., Gupta, N., & Gupta, R. (2018). HIGH SPEED ADDER USING GDI TECHNIQUE. International Journal of Engineering Technologies and Management Research, 5(2), 130-136. https://doi.org/10.29121/ijetmr.v5.i2.2018.634