• Sandeep Singh M.Tech Student, Amity School of Engineering & Technology, India
  • Neeraj Gupta Assistant Professor, Amity School of Engineering & Technology, Amity University Haryana, Gurugram, India
  • Rashmi Gupta Assistant Professor, Amity School of Engineering & Technology, Amity University Haryana, Gurugram, India
Keywords: Leakage Current, Dynamic Power Dissipation, CMOS, Clock Gating, Parallelism


In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.


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How to Cite
Singh, S., Gupta, N., & Gupta, R. (2018). LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES. International Journal of Engineering Technologies and Management Research, 5(2), 223-232. https://doi.org/10.29121/ijetmr.v5.i2.2018.648