FPGA-BASED ANALYSIS AND PERFORMANCE EVALUATION OF FIR FILTERS

Vidhya D S.; Ishan Prabhu; Sohan Sawant; Melba d’souza; Sagar Shetkar

doi:10.29121/shodhkosh.v5.i6.2024.5653

Authors

Dr. Vidhya D S. Associate Professor, Don Bosco College of Engineering, Goa University, Goa
Ishan Prabhu Student, Don Bosco College of Engineering, Goa University, Goa
Sohan Sawant Student, Don Bosco College of Engineering, Goa University, Goa
Melba d’souza Assistant Professor, Don Bosco College of Engineering, Goa University, Goa
Sagar Shetkar Student, Don Bosco College of Engineering, Goa University, Goa

DOI:

https://doi.org/10.29121/shodhkosh.v5.i6.2024.5653

Keywords:

Dsp Blocks, Fpga, Fir Filter

Abstract [English]

Finite impulse response (FIR) filters are widely used in digital signal processing because of their many benefits. Because these filters are naturally stable, stability issues during design and implementation are resolved. FIR filters have historically been made using ASICs or DSP processors. On the other hand, the incorporation of specialized DSP blocks and fundamental characteristics like re-configurability, reusability, cost effectiveness, and scalability have made FPGAs a preferred platform for the implementation and testing of digital signal processing systems. Optimized convolution algorithms can effectively realize FIR filters, even though they usually require a high order. The main goal of this project is to implement the FIR filter design on an FPGA. Traditional FIR filter design methods often have limitations in terms of processing delay, memory usage, power consumption, and overall system performance. To address these problems, this project uses the Distributed Arithmetic with Offset Binary Coding (DA-OBC) technique. By enabling high-speed operation and lowering hardware resource consumption, this technique improves performance while minimizing circuit complexity. Verilog HDL was used to design the FIR filter, which was then implemented using the Xilinx ISE Design Suite 14.7. MATLAB was used to generate the filter coefficients, allowing for accurate and effective filter design.

References

P. Kollig, B. Al-Hashimi, and K. Abbott, “Fpga implementation of high performance fir filters,” in 1997 IEEE International Symposium on Circuits and Systems (ISCAS),vol. 4, 1997, pp. 2240–2243 vol.4. DOI: https://doi.org/10.1109/ISCAS.1997.612767

S. Mirzaei, A. Hosangadi, and R. Kastner, “Fpga implementation of high speed fir filters using add and shift method,” in 2006 International Conference on Computer Design, 2006, pp. 308–313. DOI: https://doi.org/10.1109/ICCD.2006.4380833

T.-T. Do, H. Kropp, C. Reuter, and P. Pirsch, “A flexible implementation of high performance FIR filters on Xilinx FPGAs,” in Field-Programmable Logic and Applications (FPL), Lecture Notes in Computer Science, vol. 1482, Springer, 1998, pp. 441–445. DOI: https://doi.org/10.1007/BFb0055277

R. R. Sudharsan, “Synthesis of fir filter using adc-dac: A fpga implementation,” in 2019 IEEE International Conference on Clean Energy and Energy Efficient Electronics Circuit for Sustainable Development (INCCES), 2019, pp. 1–3. DOI: https://doi.org/10.1109/INCCES47820.2019.9167696

G. Jinding, H. Yubao, and S. Long, “Design and fpga implementation of linear fir low-pass filter based on kaiser window function,” in 2011 Fourth International Conference on Intelligent Computation Technology and Automation, vol. 2, 2011, pp. 496–498. DOI: https://doi.org/10.1109/ICICTA.2011.408

S. Bhattacharjee, S. Sil, and A. Chakrabarti, “Evaluation of power efficient fir filter for fpga based dsp applications,” Procedia Technology, 2013 vol. 10, pp.856–865 DOI: https://doi.org/10.1016/j.protcy.2013.12.431

X. Jiang and Y. Bao, “Fir filter design based on fpga,” in 2010 International Conference on Computer Application and System Modeling (ICCASM 2010), vol. 13, 2010, pp. V13–621–V13–624. DOI: https://doi.org/10.1109/ICCASM.2010.5622482

M. Shil, H. Rakshit, and H. Ullah, “An adjustable window function to design an fir filter,” in 2017 IEEE International Conference on Imaging, Vision & Pattern Recognition (icIVPR), 2017, pp. 1–5. DOI: https://doi.org/10.1109/ICIVPR.2017.7890865