VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH

  • Dr. Anuradha M. Sandi Department of Electronics and Communication Engineering, Guru Nanak Dev Engineering Collage, India
Keywords: VLSI Design, Propagation Delay, Carry Generator, Carry Propagator, Ripple Carry Adder

Abstract

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

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Published
2019-06-30
How to Cite
Sandi, A. (2019). VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH . International Journal of Engineering Technologies and Management Research, 6(6), 40-50. https://doi.org/10.29121/ijetmr.v6.i6.2019.392