• Sathish K Department of Electronics & Communication Engineering, SRM University, INDIA
  • Aswinkumar R Department of Electronics & Communication Engineering, SRM University, INDIA
  • Theresal T Department of Electronics & Communication Engineering, SRM University, INDIA
  • Dhanabal S Department of Electronics & Communication Engineering, Periyar Maniammai University, INDIA



Reversible Logic, Reversible Decoder, GLG Gate


Nowadays, It became the fashion among the researchers about creating the New Reversible Gates. In the Reversible Literature, already many gates are proposed but it is the first time to propose a Gate for a decoder(Data Distributor). The proposed GLG (Garbage Less Gate) has No Garbage output which denotes its power efficiency. In this paper 2:4 reversible decoder is constructed using GLG. The proposed gate is also extended to N:2N decoder using the proposed GLG Gate and the Fredkin Gate. The theoretical proposition is verified through Optisystem & Modelsim Software. A comparison with existing reversible decoders is also included.


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A.Barenco, C.H. Bennett, R. Cleve, D.P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, lA. Smolin, H. Weinfurter,"Elementary gates for quantum computation", Phys. Rev. A 52 (5) (1995) 3457-3467. DOI:

Phillip Kaye, Raymond Laflamme, Michele Mosca "An Introduction to Quantum Computing" Oxford University Press Jan 2007eBook-LinG, ISBN 0-19-857000-7

T.Toffoli, "Reversible computing", Tech memo MIT/LCS /TM-151, MIT Lab for Computer Science (1980). DOI:

E. Fredkin and T. Toffoli, "Conservative logic", Int. 1. Theo. Phys., 21 (1982) 219. DOI:

Theresal T ,Sathish K and Aswinkumar R, “ An Optimized Implementation of all Reversible Logic Gates using newly designed ALL GATE”, published at “ International Journal of Science and Innovative Engineering and Technology, Volume 2, May Issue 2015 Edition”.

Sathish K, Aswinkumar R, Theresal T, Maivezhi Raja L, “A Low Power Reversible Braun Array Multiplier Architecture using KTR Gate” –Published at “International Journal of Emerging Trends in Engineering and Development, Volume 4, Issue 5, June-July 2015 Edition”.

Sathish K, Aswinkumar R, Theresal T, Bala Murugan T, “A Reversible Logic based Power Efficient N*1 Multiplexer Design using SRM Gate” –Published at “International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 6, June 2015 ”.

M. Morris Mano, Computer System Architecture, Pearson.

M. Shamsujjoha, and H. M. H. Babu, ”A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor,” 2013 26th International Conference on VLSI Design and the 12th International Conference on Embedded Systems, pp. 368 – 373, 2013. DOI:

S. K. Noor Mahammad, S. K. Sastry Hari, S. Shroff, and VKamakoti, “Constructing online testable circuits using reversible logic”, Proceedings of the 10th IEEE VLSI Design and Test Symposium (VDAT), Goa, India, August 2006, pp. 373-383.

R. Aradhya, R, Chinmaye, and K. Muralidhara, “Design, Optimizationand Synthesis of Efficient Reversible Logic Binary Decoder,”International Journal of Com-puter Applications, vol. 46, pp. 45-51,2012.

Poodari Sairam Goud, Naveen Kumar, Reversible Applications of Decoder and Its Applications, International Journal & Magazine of Engineering, Technology, Management and Research Volume No: 1(2014), Issue No: 12 December 2014 Page 251.

C. Taraphdara, T. Chattopadhyay, and J. Roy, “Mach-zehnder interferometer-based alloptical reversible logic gate,” Optics and Laser Technology, vol. 42, no. 2, pp. 249–259, 2010 DOI:




How to Cite

K, S., R, . A., T, T., & S, D. . (2015). ALL OPTICAL REVERSIBLE DATA DISTRIBUTOR . International Journal of Engineering Technologies and Management Research, 2(1), 1–11.