DESIGN OF RISC PROCESSOR USING VHDL

The aim of the paper is to design a 16-bit RISC processor. It is having five stage pipelining which is designed using VHDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Number of instructions are designed for this processors. Multiplier is also designed using ADD instruction. Proposed instructions are simulated using Xilinx ISE 13.1i. The processor is synthesized using Spartan3A XC3S50A XILINX Tool.


INTRODUCTION
The processors are characterized by nature of their instruction set architecture. There are basically two ways of designing instruction sets CISC and RISC. RISC stands for reduced instruction set computer. It has faster and simpler set of instructions. The main feature of RISC is a pipeline. It has simple addressing modes and fixed length of instructions. RISC processor reduces cycles per instruction at the cost of a number of instructions per program. Reduced instructions in RISC require less number of transistors. RISC is used in portable devices such as Apple iPod due to its power efficiency.
CISC is a complex instruction set computer. It has a complex instruction set so decoding becomes complex. One instruction supports many addressing modes. CISC minimizes the number of instructions per program at a cost of a number of cycles per instruction. Examples of CISC are IBM 370/168 it's a 32-bit processor introduced in 1970, VAX 11/780, Intel 80486 it's a processor with 233 instructions and of varying length launched in 1989.
Pipelining is a key feature of RISC in which processor works on different stages of instruction at the same time to execute more instructions in shorter time. The different stages of pipelines are instruction fetch, decode, execute, memory and write back. Pipelining improves throughput by working on many operations at the same time. Different processors have a different number of stages of the pipeline. The length of pipeline depends on the longest stage. Five stage pipelined processor is nearly five times faster than the non-pipelined processor. Pipelining gives highperformance processors. VHDL is used for designing processor which is a parallel programming language. The proposed processor has five stage pipelining and it is 16 bit i.e. it operates on 16bit data. It has eight registers. As it is a RISC processor an instruction takes one clock to complete. It is simulated in Xilinx 13.1i ISE using VHDL and synthesized using Spartan-3A XC3S50A XILINX tool.

RELATED WORK
In this paper, a 16-bit RISC processor designed using VHDL where behavioral programming is used to model basic units. It is a four stage pipelined processor. Pipelining improves clock cycles per instruction. All the hazards were removed and design is implemented on FPGA [1].
In 2009 Kui YI, Yue-Hua DING designed a 32-bit RISC processor based MIPS. It is a five-stage pipelined processor. A top-down approach is used to design and language used is VHDL. It is easy to debug and simulated successfully on QuartusII [2].
In this paper, instruction fetch unit & decode unit are designed for reduced instruction set computer Processor. It is simulated on QuartusII successfully [3].
In this paper, a 32-bit RISC processor has been designed using VHDL. The reduced instruction set computer has simple decoding as it has all instructions of same length. It also has faster instructions. In the paper, the results are compared with previous processors [4].

3.1.INSTRUCTION SET ARCHITECTURE
The words of computer's language are instructions and its vocabulary is instruction set.

A. Instruction Formats
Instruction format is a collection of fields of binary numbers. The instructions of proposed processor have 3 formats Register-Type, Immediate-type, Jump-type given in figures below.  OR Rs, Rt, Rd

1) R-Type Format
In the above instruction values of registers, Rt and Rs are added and the result is stored in destination register Rd.
2) I-Type Format MOV Rd, #data In the above instruction, #data is moved in Rd. Rd gives the address of destination register. #data is 16-bit data.

JMP Addr
The above instruction is unconditional jump instruction. Addr is an address where a branch takes place. Some conditional jumps are also present which takes place when a particular condition is true.

B. Instruction Set
All the instructions of proposed processor are 32-bit in length. Instructions have different addressing modes. Instruction formats are different for different instructions. The proposed processor has eight registers REG1, REG2, REG3, REG4, REG5, REG6, REG7 and REG8 each 16-bit wide. The processor supports register addressing, immediate addressing, register immediate addressing modes.

3.2.DATAPATH
The data path is a collection of different functional units. It gives required elements for execution of the particular instruction. It differs according to the type of instruction. The proposed processor has three types of the data path. The data path and control unit together forms CPU. The data path elements are nothing but functional units. Such as instruction memory, ALU, PC.
A. R-Format Data Path  B. RI-Format Data Path Fig. 6 shows register immediate format data path. The first instruction is fetched from program memory. One operand is read from the register file and other is directly given in the instruction so this mode is register immediate data path. In earlier data path both the operands are read from the register file only with given addresses. Here one operand is directly provided in the instruction itself.

CONCLUSION
The proposed 16-bit RISC processor is designed using a parallel programming language called VHDL. It is simulated and synthesized using Xilinx ISE 13.1i. All instructions are simulated successfully. Simulation results show that the proposed processor is working correctly. The proposed processor has a delay of 4.744 ns and operating frequency of 210.775 MHz. when the proposed work compared with previous processors, it can be seen that proposed processor has less delay.

ACKNOWLEDGEMENT
I would like to thank my guide Prof. S. D. Mali for his support and guidance in fulfillment of this work. I am grateful to him for his constant encouragement and valuable guidance. This work is a combined effect of efforts put in by me and my guide. I would also like thank all those who are part of this work.