@article{Sharma_Gupta_Gupta_2018, title={POWER REDUCTION TECHNIQUES IN VLSI}, volume={5}, url={https://www.granthaalayahpublication.org/ijetmr-ojms/ijetmr/article/view/IJETMR18-CINSP-18}, DOI={10.29121/ijetmr.v5.i2.2018.633}, abstractNote={<p><em><strong>The paper investigates different level of techniques used for power reduction in VLSI. Before,</strong></em><br><em><strong>most of the researches were oriented towards bringing about high speed and miniaturization.</strong></em><br><em><strong>At present, because of the increasing trend of compact devices, the requirement for low power</strong></em><br><em><strong>consuming circuits have also increased. This necessitates the need to align the research for</strong></em><br><em><strong>reducing power dissipation in VLSI circuits. In the given paper we will briefly discuss about</strong></em><br><em><strong>the different types of power reduction techniques at design abstraction level which are adopted</strong></em><br><em><strong>in industries now-a-days. The comparison of traditional techniques and present techniques</strong></em><br><em><strong>are also covered in this paper.</strong></em></p>}, number={2}, journal={International Journal of Engineering Technologies and Management Research}, author={Sharma, Mehar and Gupta, Neeraj and Gupta, Rashmi}, year={2018}, month={Feb.}, pages={123–129} }