POWER REDUCTION TECHNIQUES IN VLSI

  • Mehar Sharma M.Tech Student, Amity School of Engineering & Technology, India
  • Neeraj Gupta Assistant Professor, Amity School of Engineering & Technology Amity University Haryana, Gurugram, India
  • Rashmi Gupta Assistant Professor, Amity School of Engineering & Technology Amity University Haryana, Gurugram, India
Keywords: Gating Technique, Back Biasing, FET, Multi-Threshold Devices, Power Dissipation

Abstract

The paper investigates different level of techniques used for power reduction in VLSI. Before,
most of the researches were oriented towards bringing about high speed and miniaturization.
At present, because of the increasing trend of compact devices, the requirement for low power
consuming circuits have also increased. This necessitates the need to align the research for
reducing power dissipation in VLSI circuits. In the given paper we will briefly discuss about
the different types of power reduction techniques at design abstraction level which are adopted
in industries now-a-days. The comparison of traditional techniques and present techniques
are also covered in this paper.

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Published
2018-02-28
How to Cite
Sharma, M., Gupta, N., & Gupta, R. (2018). POWER REDUCTION TECHNIQUES IN VLSI. International Journal of Engineering Technologies and Management Research, 5(2), 123-129. https://doi.org/10.29121/ijetmr.v5.i2.2018.633