MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR “MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR.”

: In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of MOS/SET hybrid circuits will be developed. As a result of this, a functional model for the single-electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed hybrid MOS. The SET model can be easily coded in any hardware description language .


Introduction
The scaling down of the sizes of MOSFETs has been the basis of the development of the semiconductor industry for the last 30 years (Shagun Pal et al., 2013). However, in the early years of the 21st century, the scaling of CMOSFETs is entering the deep sub-50 nm regime (Goyal et al., 2015). In this deep-nanoscaled regime, fundamental limits of CMOSFETs and technological challenges with regard to the scaling of CMOSFETs are encountered (Mittal, 2013). On the other hand, quantum-mechanical effects are expected to be effective in these small structured devices. Therefore, in order to extend the prodigious progress of LSI performance, it is essential to introduce a new device having an operation principle that is effective in smaller dimensions and which may utilize the quantum-mechanical effects, and thus provide a new functionality beyond that attainable with CMOSFETs. Single-electron devices are promising as  new nanoscaled devices because single-electron devices retain their scalable property and  moreover, they can manage the motion of a single electron (Krishnan, 2014). Therefore, if the single-electron devices are used as ULSI elements, the ULSI will have the attributes of extremely high integration and extremely low power consumption. The utilization of single electron devices in ULSIs is expected to reduce the power consumption of ULSIs. SET is said to be the tiny transistor with tiniest power consumption." SETs are necessary for ULSI design. Unlike FET, SET have quantum trend which is known as Tunnel effect. The organization of SETs is given in Figure 1.  In this the one island which are capatively coupled to gate electrode. The total capacitance of the island is given by: Thus, the setup is called single electron transistor.

Principle of Single Electron Tunneling and Coulomb Blockade Effect
Size reduction goes along with a reduction of capacitances. For a plate capacitor of area L 2 at a separation L its capacitance C scales with L. As a consequence, the quantization of charge can dominate the behavior of circuits, in which tunnelling of single electrons carries the current. The tunnel junction capacitor is charged with one elementary charge by the tunnelling electron, causing a voltage buildup U=e/C, where e is the elementary charge of 1.6×10−19 coulomb and C the capacitance of the junction. If the capacitance is very small, the voltage buildup can be large enough to prevent another electron from tunnelling. As shown in Figure 4 & 5 a tunnel junction is measured as a thin insulating hurdle between two conducting electrodes. The electrostatic energy (Ec) is given by Where C is the capacitance of the island.
The suppression of electron transfer can be removed by one of these two cases: (a) When the blockade energy is overcome by using thermal excitations at a temperature T: (b) When the blockade energy is overcome by using an externally applied voltage V: V~Vt= Ec/e=e/2C Where, Vt is known as threshold voltage.

I-V Characteristics of SET
In Figure 6(a) shows the I-V characteristics for the symmetric junction circuit of single electron transistor where C1=C2 and R1=R2. In this situation region, the junction behaves like a resistor. The Fig. 6(b) represent the I-V characteristics for a highly asymmetric junction circuit for R1<<R2. In this case, the charge carriers, electrons enter through one junction and then run away to second junction due to the presence of high resistance.

Objectives of the Study
In microelectronic industry, making things smaller is the most valuable point, since smaller feature size implies higher computation power per unit area as well as lower cost. The study has four objectives: 1) Modeling & designing of single electron transistor (SET) architectures.
2) To further reduce circuit area and power dissipation by utilizing SET's unique Coulomb blockade oscillation characteristic. 3) To improve the reliability of SET-based circuits against background charges (BCs) by using different circuit structures. 4) Implementation of Switched Capacitor Filter using the designed SET.

Scope of the Study
Now a day a lot of research papers have been proposed on Single Electron Transistors and its application in different field of electronics which clearly describes its importance in future electronics industry. After a decade or so it will become one of the most promising device after the evolution of MOSFET. But there are still some areas left which has to be further explored for the final implementation in the electronics field such as fabrication and modelling of SETs. But recently fabrication is also started. Interestingly one more problem in which most researchers are excited to do research is of Quantum dot. It is one of the main elements of the SET and in the today's scenario most of the research papers are proposed in this field of SET. In the recent past Switched Capacitor Filter is used extensively for the increasing the gain and in other electronics circuits. But due to the limitation of MOS fabrication a new version of Filter are required which have a low power consumption, high operating speed and fast throughput.

Proposed Plan of Work (Methodology)
In the early days of microelectronic design, a top-to-down design flow was conceived to achieve the designs, while a bottom-up verification path was used in order to check them during every stage of design with the aim of generating a series of EDA tools. In a near future, hybrid systems composed of nanometric CMOS transistors and nano-devices, such as the SET will also need the development of a counterpart of their own design and verification paths. It is regarding the last one, that a simulation methodology is devised in order to determine their electric response. The main current obstacle when establishing a simulation strategy of hybrid systems consists in dealing with the big gap in development of both worlds, that is to say, the simulation methodology for CMOS circuits is mature even considering the new issues regarding the nanometric dimensions of the devices; while the simulation methodology for SET structures is still in its infancy. A simulation methodology for hybrid systems must cope with this circumstance while providing a reliable verification of the electric behaviour of the MOS/SET circuitry in a scheme that should be appealing for nowadays circuit designers. By considering this aspect, a particularly straightforward verification strategy for hybrid systems composed of SET devices and CMOS consists in establishing models for the SET that can be easily combined with the MOS models that are embedded in SPICE-like simulators. The methodology for simulating hybrid circuits is graphically described in the flow diagram of Figure 10. Hereafter, a step-by-step explanation of the blocks of the methodology is given.  Now we design the novel circuit with the help of Single Electron Transistor for microelectronics appliance and compare its characteristics with the conventional CMOS Technology.

Expected Outcome of the Study
A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of SET circuits will be developed. As a result of this, a functional model for the single electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed SET. The SET model can be easily coded in any hardware description language.