1.
Sharma M, Gupta N, Gupta R. POWER REDUCTION TECHNIQUES IN VLSI. Int. J. Eng. Tech. Mgmt. Res. [Internet]. 2018 Feb. 28 [cited 2024 May 22];5(2):123-9. Available from: https://www.granthaalayahpublication.org/ijetmr-ojms/ijetmr/article/view/IJETMR18-CINSP-18